The present invention relates to high-speed integrated circuit logic. In particular, the present invention relates to gallium arsenide logic integrated circuits.
As the gate count on a digital IC chip increases, the power dissipation per logic gate must decrease. This is because the chip temperature rise due to the total power dissipated must not exceed the limit set by reliability and performance considerations. It is generally known the the power dissipation, P.sub.d, of a depletion mode MESFET logic gate decreases rapidly with the magnitude of the pinch-off voltage, V.sub.p, that is, P.sub.d varies as the approximate magnitude of V.sub.p.sup.2. However, two problems arise when reduction of pinchoff voltage is used for reducing the power dissipation. First, can the sigma over mu (variance over mean) spreads of the devices' electrical characteristics be maintained reproducibly over large areas as the magnitude of V.sub.p is reduced? This objection may become less serious as material and processing technologies improve in the future. Second, the relationship between bit-error-rate (BER) and the combination of signal noise margin and clock rate is not known. Since it is reasonable to assume that the BER increases rapidly with decreasing noise margin, it could become the dominant factor in the decision making process for selecting V.sub.p for many applications.
The present invention provides a GaAs MESFET logic gate which consumes significantly less power and is faster than the more conventional BFL and SDFL logic gates. The gate uses depletion mode FET's and is a static one.
Thus, it is an object of the present invention to provide a gallium arsenide logic technology wherein power dissipation is reduced without sacrificing the speed of prior art logic technologies.
Gallium arsenide MESFET logic provides roughly triple the speed of silicon MESFET logic, for similar circuit dimensions, but power dissipation is a substantially worse problem in gallium arsenide. Similar speed advantages may be obtained in other III-V materials, but power dissipation remains a great problem.
It is a further object of the present invention to provide a III-V depletion mode MESFET logic gate which improves the speed of prior art III-V depletion mode MESFET logic gates with no increase in power dissipation. It is a further object of the invention to provide a gate which improves the power dissipation of prior art III-V depletion mode MESFET logic gates, without sacrificing the speed of the prior art designs.
Depletion mode gallium arsenide MESFET technology has the further advantage of relatively mature and familiar processing techniques, as well as familiarity to logic designers.
The conventional depletion mode GaAs MESFET logic gate, first introduced by Van Tuyl and Liechti [1] is shown in FIG. 1. This cell type is frequently referred to as a buffered FET logic (BFL) gate. The cell has a logic branch and a voltage level shifter circuit. For optimum speed performance, the branches are designed to have nearly equal response times. The arrangement shown in FIG. 1 dissipates approximately 50 mW at standard bias voltages, about 80% of which is dissipated in the VS branch. As shown at the bottom of FIG. 1, the cell has a low-pass filter type response.
FIG. 2 shows the capacitively coupled logic (CCL) gate proposed by Livingstone and Mellor infra. This cell has a bandpass filter type response and, consequently, must be operated above the lower cutoff frequency f.sub.cl. The f.sub.cl is typically about 6 kHz (depending on the particular layout employed). The upper cutoff-frequency, f.sub.cu, is about 35% greater than that of the BFL cell of equal width for unity fan-out (FO). This advantage decreases with FO. The measured power dissipation of the 50 micron wide cell fabricated was approximately 20 mW for V.sub.p =-2.5 V which scales to approximately 8 mW for 20 micron wide cells. The main disadvantage of the CCL cell is that (due to the low-frequency cutoff) it must be initialized before proper operation can proceed. Accordingly, for many applications, its use will require additional initialization and refresh circuitry.
Thus, it is an object of the present invention to provide a gallium arsenide logic gate which has high speed and low power dissipation.
It is a further object of the present invention to provide a gallium arsenide logic gate which has high speed and low power dissipation, and does not require initialization or refresh cycles.
To accomplish these and other objectives, the present invention provides a logic cell wherein the logic switch node, i.e., a node which is selectively pulled down by one or more transistors controlled by the input signal(s), is coupled both by a DC circuit (preferably a voltage level shifter circuit) and also by a separate AC circuit (preferably a feed-forward capacitor) to the output node. This provides both the desirable high-frequency characteristics permitted by capacitative coupling, and the DC response provided by the use of the voltage level shifter circuit. Moreover, since the cell has DC response, initialization and refresh cycles are not necessary. Since the feed-forward capacitor will carry a substantial part of the logic signal, the width of the devices in the voltage level shifter circuit can be reduced. This greatly reduces power dissipation in the device.
The following publications provide useful background information on gallium arsenide logic gates, and all of them are hereby incorporated by reference:
R. L. Van Tuyl and C. A. Liechti, "High-speed integrated logic with GaAs MESFET's," in ISSCC Dig. Tech. Papers, p. 114, 1973. See also R. L. Van Tuyl, C. A. Liechti, R. E. Lee, and E. Gowen, "GaAs MESFET logic with 4 GHz clock rate," IEEE J. Solid-State Circuits, SC-12, p. 485, 1977. See also by same authors, "Gallium Arsenide spawns speed," IEEE Spectrum, vol. 14, p. 40, March 1977.
B. M. Welch and R. C. Eden, "Planar GaAs integrated circuits fabricated by ion implantation," in IEDM Dig. Tech. Papers, p. 205, 1977. See also R. C. Eden, B. M. Welch, R. Zucca, and S. I. Long, "The prospects of ultrahigh-speed VLSI GaAs digital logic," IEEE Trans. Electron Devices, ED-26, p. 299, 1979.
A. W. Livingstone and P. J. T. Mellor, "Capacitor coupling of GaAs depletion mode FET's," 1980 GaAs IC Symposium Abstracts, paper no. 10.
M. R. Namordi and W. M. Duncan, "The effect of logic cell configuration, gatelength, and fan-out on the propagation delays of GaAs MESFET logic gates," IEEE Trans. Electron Devices, ED-29, p. 402, 1982.
R. Van Tuyl and C. A. Liechti, "Gallium Arsenide digital integrated circuits," Technical Report AFAL-TR-74-40 to Air Force Avionics Laboratory, WPAFB, March, 1974.